%FILENAME%
vtr-8.0.0-4-x86_64.pkg.tar.zst

%NAME%
vtr

%BASE%
vtr

%VERSION%
8.0.0-4

%DESC%
Verilog to Routing -- Open Source CAD Flow for FPGA Research

%CSIZE%
6525293

%ISIZE%
20454327

%MD5SUM%
b1c9e264e765bb9e496a87906ac243a5

%SHA256SUM%
9faba96d6ecb95d5e5af5e542690f0075d0bc57d1f046b13562de7f167e4792e

%PGPSIG%
iQIzBAABCAAdFiEEiJtevd1QWmg2IZANrx0hme8KPM8FAmS3CtsACgkQrx0hme8KPM948w//eju0XnJIXbOqRbFfu14MxzR7bglQcQ/gfY6RJCVM9HMlAALVYNQca8PTMy2grLWSxMfm4Ij1FLAXyMkQZueFhXkk1t4a0xcQiWwyUlnkrzh1EfE+RZqXj2uX2fdOjPKwiPC1XI3a7BxtYKmf4WnK6IUeWPbmFnhl64R5F8FkTadDmd68WT59xUXirl5FpEUnOoUU/1FTgvmwDb6cvNJm4PzSsB9nC+UD1yUybPuXWSB9805ilVB52c0LcHxQlcEKjberNXNv9b6pf9fmb3cY0OJcbAlG3Pqflg7lIlKrA7YHZQ/lVJb4VB7Edae/ph6IYdtkeDkYP6yJy/S3liAuUUiGc0+PTcZ0B+SHVKIbguxViyNBIKfdTPUbFK2GxsxIRBTxcRuT4IC/6l5TwjaPk9KUM2Gj15ay7OROgOKE+Z3YnU+5FyLBGBJqlKJFVnIxu0AeVqggiitn2vSyfpxsVxJgm+fU9v4mBx15MPTY/WjHnSdnz4gqs383xMfWi9rE5C5ubnbUrlTSPWdyijoQJLH9ENmPVZ9V8jjv1zmJsKnMDoK8qwxG7x3sfSIQktDF4OZ9BsJaMh0lX5TtpwQLxwihfQ71LD2Y8LNbnXNnBkNH9X6V8ILOCpNHlmbBig+L57h0IoSyl0czsua/PwYT6Ple7s2g5bq9uMrKfqnCSP4=

%URL%
https://verilogtorouting.org

%LICENSE%
MIT

%ARCH%
x86_64

%BUILDDATE%
1637948324

%PACKAGER%
Antonio Rojas <arojas@archlinux.org>

%DEPENDS%
ctags
tbb

%MAKEDEPENDS%
cmake

